Method for manufacturing a stacked semiconductor package, and stacked semiconductor package

ABSTRACT

A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Division of application Ser. No. 12/249,025 filedon Oct. 10, 2008, which is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2007-266307, filed onOct. 12, 2007; the entire contents of both of which are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

Various attempts are made so as to satisfy the requirements ofincreasing the capacity of a semiconductor memory and developing thefunction of the semiconductor memory. With the increase of the capacitorof the semiconductor memory, a plurality of thinner semiconductor chipsare prepared and stacked so as to increase of the total capacity of thesemiconductor memory in addition to the increase of the capacity of thesemiconductor chip constituting the semiconductor memory. With thedevelopment of the semiconductor memory, a plurality of semiconductorchips with respective different functions are prepared and stacked torealize a semiconductor memory which can exhibit different functions.

In a conventional stacked semiconductor package where a plurality ofsemiconductor chips are stacked as described above, one or more of thesemiconductor chips are electrically connected with a board by means ofwiring and the semiconductor chips are electrically connected with oneanother by means of wiring. In the wiring electric connection, however,the wires to be used are shaped in loop so as to prevent unnecessaryelectric connection with other parts (such as the corner of eachsemiconductor chip) except the electrodes and the occurrence of leakcurrent. As a result, the total thickness of the semiconductor packageis increased.

In this point of view, it is proposed that the semiconductor chips areelectrically connected with one another by a wiring layer formed at theside of the stacking structure of the semiconductor chips (e.g., referto JP-A2004-63569 (KOKAI)). In this case, however, in order to preventthe electric connection between other parts of the semiconductor chipsexcept the electrodes thereof, particularly between the side of thestacking structure of the semiconductor chips and the wiring layer, aninsulating layer is formed between the side of the stacking structureand the wiring layer so as to form the electric insulation between theside of the stacking structure and the wiring layer.

However, after the semiconductor chips are stacked, the insulating layeris formed per semiconductor chip. Concretely, the insulating layer isformed at the side of each semiconductor chip. Therefore, it is requiredthat the forming process of the insulating layer is carried out for allof the semiconductor chips to be stacked. Since the number of theforming process of the insulating layer is increased as the number ofthe semiconductor chips to be stacked is increased, the manufacturingprocess of the stacked semiconductor package becomes complicated as awhole so as to increase the manufacturing cost of the stackedsemiconductor package.

Moreover, since the insulating layer is made of a thermosetting resin,it is required that the assembly under construction including the boardis thermally treated as a whole. As a result, the assembly suffers fromthe thermal treatment several times so that the board and/or one or moreof the semiconductor chips may be warped and the characteristics of oneor more of the semiconductor chips may be changed.

In the stacking of the semiconductor chips, the adjacent ones of thesemiconductor chips are bonded with one another with adhesive. In thiscase, however, the adhesive may be peeled off by the several thermaltreatments so that the adjacent ones of the semiconductor chips areimperfectly bonded with one another.

BRIEF SUMMARY OF THE INVENTION

An aspect of the present invention relates to a method for manufacturinga stacked semiconductor package where a plurality of semiconductor chipsare stacked on a substrate, including: forming insulating layers atportions of a wafer corresponding to sides of the plurality ofsemiconductor chips when the plurality of semiconductor chips are in thewafer;

processing the wafer so as to obtain the plurality of semiconductorchips; subsequently stacking the plurality of semiconductor chips on thesubstrate such that the insulating layers formed at the sides of theplurality of semiconductor chips are respectively positioned at the sameside as one another; and forming a wiring over the insulating layersformed at the sides of the plurality of semiconductor chips so that theplurality of semiconductor chips are electrically connected with oneanother and one or more of the plurality of semiconductor chips areelectrically connected with the substrate.

Another aspect of the present invention relates to a stackedsemiconductor package, including: a substrate; a plurality ofsemiconductor chips subsequently formed on the substrate and havingrespective insulating layers at sides thereof such that the insulatinglayers of the plurality of semiconductor chips are positioned at thesame side as one another; and a wiring formed over the insulating layersat the sides of the plurality of semiconductor chips so that theplurality of semiconductor chips are electrically connected with oneanother and one or more of the plurality of semiconductor chips iselectrically connected with the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 4, 6, 7 and 8 are cross sectional views showing a first stepin the forming method of a stacked semiconductor package according to anembodiment.

FIG. 5 is a cross sectional view showing a step modified from the stepshown in FIG. 4.

FIG. 9 is a cross sectional view showing a step modified from the stepshown in FIG. 8.

FIGS. 10 and 11 are cross sectional views showing a stackedsemiconductor package according to an embodiment.

FIGS. 12 to 14 are cross sectional views showing a first step in theforming method of a stacked semiconductor package according to a secondembodiment.

FIG. 15 is a cross sectional view showing a step after the step shown inFIG. 14.

DETAILED DESCRIPTION OF THE INVENTION

Some embodiments will be described with reference to the drawings.

In a conventional method for manufacturing stacked semiconductor chips,after the semiconductor chips are stacked, the insulating layer isformed per semiconductor chip. Concretely, the insulating layer isformed at the side of each semiconductor chip. Therefore, it is requiredthat the forming process of the insulating layer is carried out for allof the semiconductor chips to be stacked. Since the number of theforming process of the insulating layer is increased as the number ofthe semiconductor chips to be stacked is increased, the manufacturingprocess of the stacked semiconductor package becomes complicated as awhole so as to increase the manufacturing cost of the stackedsemiconductor package.

Moreover, since the insulating layer is made of a thermosetting resin,it is required that the assembly under construction including the boardis thermally treated as a whole. As a result, the assembly suffers fromthe thermal treatment several times so that the board and/or one or moreof the semiconductor chips may be warped and the characteristics of oneor more of the semiconductor chips may be changed.

In the stacking of the semiconductor chips, the adjacent ones of thesemiconductor chips are bonded with one another with adhesive. In thiscase, however, the adhesive may be peeled off by the several thermaltreatments so that the adjacent ones of the semiconductor chips areimperfectly bonded with one another.

First Embodiment

FIGS. 1 to 9 relate to the manufacturing process of a stackedsemiconductor device according to a first embodiment. In the drawings,attention is paid to a portion of a wafer so as to clarify thedistinctive features of the first embodiment. The portion of the waferto which attention is paid is enlargedly depicted.

As shown in FIG. 1, electrodes 11 are formed of electric conductor suchas aluminum on a wafer 10 made of, e.g., silicon, and first trenches 10Aare formed at the area except the electrodes 11 of the wafer 10 by meansof so-called dicing before grinding (DBG) so as not to penetrate thewafer 10.

As shown in FIG. 2, insulating resins 12 are formed by ink-jet orprinting so as to embed the first trenches 10A. In the use of theink-jet method, the diameter of the forefront of the nozzle is set to apredetermined size so that the insulating resin 12 is discharged for thefirst trenches 10A. In the use of the printing method, a mask with apattern in accordance with the shapes and sizes of the first trenches10A and the desired pattern to be formed is prepared, and the insulatingresins 12 are printed and formed via the mask so as to embed the firsttrenches 10A. A part of the insulating resin 12 is provided on a topsurface of the wafer with the elements being exposed.

As the insulating resin 12 may be exemplified thermoplastic resin and UVcured resin.

As shown in FIG. 3, dicing process is carried out for the insulatingresins 12 formed in the first trenches 10A to form second trenches 12Areaching to the wafer 10 throughout the insulating resins 12,respectively. Herein, since the remaining insulating resins 12 after thesecond trenches 12A are formed constitutes the insulating layers at thesides of each semiconductor chip, the second trenches 12A are formed sothat the insulating layer can be formed as designed.

In FIG. 3, the second trenches 12A are formed in V-shape. In this case,the sides 12B of the remaining insulating resins 12 are tapered by theformation of the second trenches 12A so that the rising angles of thesides 12B becomes relatively small. As described above, the remaininginsulating resins 12 constitute the insulating layers at the sides ofthe semiconductor chips and the lower portions 12C of the insulatingresins 12 constitute the lower edge portions of the insulating layers ofthe semiconductor chip (refer to, FIGS. 8 and 9).

That the rising angles of the insulating resins 12 are small means thatthe contacting angle θ of the insulating layer of the uppersemiconductor chip for the lower semiconductor chip is small (refer to,FIGS. 10 and 11). As a result, the insulating layer of the uppersemiconductor chip is smoothly contacted with the lower semiconductorchip.

Therefore, even though the wiring layers are formed over the insulatinglayers of the sides of the semiconductor chips, the wiring layers cannot be disconnected between the upper semiconductor chip and the lowersemiconductor chip.

In this embodiment, since the sides of the semiconductor chip arecovered with the insulating layers, respectively, even though thesemiconductor chips are electrically connected with one another by meansof wire bonding, the wires can not be directly contacted with thesemiconductor chips (particularly, the edges of the semiconductor chips)by the formation of the wiring layers. As a result, the manageability ofthe wires can be simplified.

The second trenches 12A may be formed in another shape except theV-shape shown in FIG. 3 as occasion demands. For example, as shown inFIG. 4, the second trenches 12A may be formed so that the insulatingresins 12 remain only at respective either sides of the first trenches10A. When the second trenches 12A are formed in V-shape as shown in FIG.3, the insulating resins 12 remain at both sides of the first trenches10A, respectively, so that both sides of the resultant semiconductorchip are covered with the corresponding insulating layers. In contrast,when the second trenches 12A are formed so that the insulating resins 12are formed at respective either sides of the first trenches 10A as shownin FIG. 4, either side of the resultant semiconductor chip is coveredwith the corresponding insulating layer.

In the former case, electric connection can be realized at both sides ofthe stacked semiconductor chips. In the latter case, electric connectioncan be realized at either side of the stacked semiconductor chips.Therefore, the second trenches 12 of V-shape as shown in FIG. 3 areeffective in the case where a plurality of semiconductor chips withrespective different semiconductor chips are stacked subsequently andthe second trenches 12 of V-shape as shown in FIG. 4 are effective inthe case where a plurality of semiconductor chips are stacked slidably.The concrete embodiment will be described below.

It is not always required that the second trenches 12A are formed so asto penetrate through the insulating resins 12, but it is required thatthe depths of the second trenches 12 are set to predetermined depthsenough to cut off and divide the wafer 10 into the semiconductor chips.

As shown in FIG. 5, a protective tape 15 is attached to the surface ofthe wafer 10 and the rear surface of the wafer 10 is grinded so as tothin the wafer 10 in a manner that the second trenches 12A are opened asshown in FIG. 6. In this way, the wafer 10 is divided into thesemiconductor chips.

As shown in FIG. 7, for example, an adhesive film 16 is attached to therear surface of the wafer 10 (divided semiconductor chips), and bycutting the adhesive film 16, the semiconductor chip(s) as shown in FIG.8 can be obtained. Herein, when the second trenches 12A are formed asshown in FIG. 4, the resultant semiconductor chip can be formed as shownin FIG. 9.

FIG. 10 is a cross sectional view showing a stacked semiconductorpackage formed by stacking the semiconductor chips as shown in FIG. 8.FIG. 11 is a cross sectional view showing a stacked semiconductorpackage formed by stacking the semiconductor chips as shown in FIG. 9.

In the stacked semiconductor package 20 shown in FIG. 10, a firstsemiconductor chip 22 is stacked on a board 21 via an adhesive layer 27,and a second semiconductor chip 23 is stacked on the center area of themain surface of the first semiconductor chip 22 via an adhesive layer28. Then, the insulating layers 24 made of the remaining insulatingresins 12 are formed at both sides of the first semiconductor chip 22,and the insulating layers 25 made of the remaining insulating resins 12are formed at both sides of the second semiconductor chip 23. Apart ofthe insulating layers 24 and 25 is provided on a top surface of thefirst semiconductor chips 22 and 23, respectively. The insulating layer24 is elongated from a top surface of the first chip 22 to a top surfaceof the board 21 via a side of the first chip 22 and the adhesive layer27. The insulating layer 25 is elongated from a top surface of thesecond chip 23 to a top surface of the first chip 22 via a side of thesecond chip 23 and the adhesive layer 27.

Moreover, wiring layers 26 are formed so as to cover the insulatinglayers 24 and 25 in a manner that electrodes 21A formed on the board 21are electrically connected with electrodes 22A and 23A formed on thesemiconductor chips 22 and 23, respectively.

On the other hand, in the stacked semiconductor package 20 shown in FIG.11, the first semiconductor chip 22 is stacked on the board 21 via theadhesive layer 27 and the second semiconductor chip 23 is stacked andshifted on the main surface of the first semiconductor chip 22 so as toexpose the end portion of the first semiconductor chip 22. Moreover, theinsulating layer 24 made of the remaining insulating resin 12 is formedat either side of the first semiconductor chip 22, and the insulatinglayer 25 made of the remaining insulating resin 12 is formed at eitherside of the second semiconductor chip 23 in the same side as theinsulating layer 24.

Then, wiring layers 26 are formed so as to cover the insulating layers24 and 25 in a manner that the electrodes 21A on the board 21 areelectrically connected with the electrodes 22A and 23A on thesemiconductor chips 22 and 23, respectively.

In the stacked semiconductor package 20 shown in FIG. 10 or 11, theinsulating layers 24 and 25 for electrically insulating between thewiring layers 26 and the semiconductor chips 22, 23 are formed beforethe semiconductor chips 22 and 23 are formed at the wafer processingprocess as described above. Namely, since the insulating layers 24 and25 are formed at the wafer processing process for forming thesemiconductor chips 22 and 23, the manufacturing efficiency of thesemiconductor chips 22 and 23 can be enhanced.

Moreover, since no thermal treatment is required when the insulatinglayers 24 and 25 are formed, various problems such as the warpages ofthe board 21 and the semiconductor chips 22, 23 and the characteristicchanges of the semiconductor chips 22, 23 due to the thermal treatmentcan be prevented. Then, the peeling-off of the adhesive layers 27 and/or28 due to the thermal treatment can be prevented so that thesemiconductor chip 22 can be sufficiently bonded with the semiconductorchip 23 and the semiconductor chip 22 can be sufficiently bonded withthe board 21.

In this embodiment, since the electric conduction between the board 21and the semiconductor chips 22, 23 can be realized by the wiring layers26 under the condition that the insulating layers 24 and 25 are formed,the stacked semiconductor package 20 can be thinned as a whole.

Instead of the wiring layers 26 shown in FIGS. 10 and 11, bonding wires,which forms an arc, may be employed to electrically connect between theboard 21 and the semiconductor chips 22, 23.

Second Embodiment

FIGS. 12 to 15 relate to the manufacturing process of a stackedsemiconductor device according to a second embodiment. In the drawings,attention is paid to a portion of a wafer so as to clarify thedistinctive features of the first embodiment. The portion of the waferto which attention is paid is enlargedly depicted.

As shown in FIG. 12, electrodes 31 are formed of electric conductor suchas copper on a wafer 30 made of, e.g., silicon, and first trenches 30Aare formed at the area except the electrodes 31 of the wafer 30 by RIE(reactive ion etching) or laser processing so as not to penetrate thewafer 30.

As shown in FIG. 13, a photosensitive member is applied onto the surfaceof the wafer 30 to form a photosensitive layer 32 so as to embed thefirst trenches 30A. The photosensitive member can be made of well knownmaterial such as photosensitive resin typified by polyimide or resist.

As shown in FIG. 14, a mask with a pattern in accordance with the shapesand sizes of the first trenches 30A and the desired pattern to be formedis prepared so that the photosensitive layer 32 is exposed and developedto form second trenches 32A at the photosensitive layer 32.

In FIG. 14, the second trenches 32A are formed so that thephotosensitive layer 32 remains at both sides of the first trenches 30A,respectively. However, the second trenches 32A may be formed atrespective either sides of the first trenches 30A, as shown in FIG. 15.

In the case that the second trenches 32A are formed as shown in FIG. 14,since the photosensitive layer 32 remains at both sides of the firsttrenches 30A,respectively, insulating layers are formed at both sides ofeach of the resultant semiconductor chips to be stacked. In the casethat the second trenches 32A are formed as shown in FIG. 15, since thephotosensitive layer 32 remains at respective either sides of the firsttrenches 30A, insulating layers are formed at respective either sides ofthe resultant semiconductor chips to be stacked.

In the former case, electric connection can be realized at both sides ofthe stacked semiconductor chips. In the latter case, electric connectioncan be realized at either side of the stacked semiconductor chips.Therefore, the second trenches 12 as shown in FIG. 14 are effective inthe case where a plurality of semiconductor chips with respectivedifferent semiconductor chips are stacked subsequently and the secondtrenches 12 as shown in FIG. 15 are effective in the case where aplurality of semiconductor chips are stacked slidably.

In FIG. 12, the first trenches 30A are shaped in inverted trapezoid. Inthis case, the rising angles of the remaining photosensitive layer 32along the side walls of the first trenches 30A become relatively small,respectively, originated from the (inverted trapezoid) shapes of thefirst trenches 30A. As described above, the remaining photosensitivelayer 32 constitutes the insulating layer(s) of the semiconductor chipas it is, and the lower portions 30C of the photosensitive layer 32constitute the lower edge portion(s) of the insulating layer(s) of thesemiconductor chip (FIGS. 8 and 9).

That the rising angles of the remaining photosensitive layer 32 alongthe side walls of the first trenches 30A are small means that thecontacting angle θ of the insulating layer of the upper semiconductorchip for the lower semiconductor chip is small (FIGS. 10 and 11). As aresult, the insulating layer of the upper semiconductor chip is smoothlycontacted with the lower semiconductor chip.

Therefore, even though the wiring layers are formed over the insulatinglayers of the sides of the semiconductor chips, the wiring layers cannot be disconnected between the upper semiconductor chip and the lowersemiconductor chip.

In this embodiment, since the sides of the semiconductor chip arecovered with the insulating layers, respectively, even though thesemiconductor chips are electrically connected with one another by meansof wire bonding, the wires can not be directly contacted with thesemiconductor chips (particularly, the edges of the semiconductor chips)by the formation of the wiring layers. As a result, the manageability ofthe wires can be simplified.

The first trenches 30A may have another shape except the invertedtrapezoid shape shown in FIG. 12 as occasion demands.

Then, a protective tape is attached to the surface of the wafer 30 andthe rear surface of the wafer 30 is grinded so as to thin the wafer 30in a manner that the second trenches 32A are opened in the same manneras FIGS. 5 to 9. In this way, the wafer 30 is divided into thesemiconductor chips. An adhesive film is attached to the rear surface ofthe wafer 30 (divided semiconductor chips), and by cutting the adhesivefilm, the semiconductor chip(s) can be obtained.

As described above, the stacked semiconductor package as shown in FIG.10 can be formed through the step shown in FIG. 14, and the stackedsemiconductor package as shown in FIG. 11 can be formed through the stepshown in FIG. 15. As a result, the stacked semiconductor packageaccording to the second embodiment can exhibit the same function/effectsas the stacked semiconductor package according to the first embodiment.

Although the present invention was described in detail with reference tothe above examples, this invention is not limited to the abovedisclosure and every kind of variation and modification may be madewithout departing from the scope of the invention.

For example, in the embodiments, the second trenches 12A or 32A areformed in addition to the first trenches 10A or 30A so as to divide thewafer into the semiconductor chips, and then, opened by grinding therear surface of the wafer. Instead of the formation of the secondtrenches 12A and 32A, for example, laser irradiation may be conductedfor the insulating resins 12 and photosensitive layer 32 formed in thefirst trenches 10A and 30A, respectively, so as to divide the wafer intothe semiconductor chips, after the first trenches 10A and 30A areembedded by the insulating resins 12 and the photosensitive layer 32,respectively.

1. A stacked semiconductor package, comprising: a substrate; a pluralityof semiconductor chips subsequently formed on the substrate and havingrespective insulating layers at sides thereof such that the insulatinglayers of the plurality of semiconductor chips are positioned at thesame side as one another; and a wiring formed over the insulating layersat the sides of the plurality of semiconductor chips so that theplurality of semiconductor chips are electrically connected with oneanother and one or more of the plurality of semiconductor chips iselectrically connected with the substrate.
 2. The stacked semiconductorpackage as set forth in claim 1, wherein the insulating layers areformed at both sides of the corresponding semiconductor chips and thewiring conducts the electric connection for the plurality ofsemiconductor chips and the substrate via the insulating layers.
 3. Thestacked semiconductor package as set forth in claim 1, wherein athickness of the insulating layer at the side thereof is greater than athickness of the insulating layer at a top thereof.
 4. The stackedsemiconductor package as set forth in claim 1, wherein the insulatinglayer is elongated from a top of the semiconductor chip to a sidethereof.
 5. The stacked semiconductor package as set forth in claim 1,wherein the semiconductor chip includes a tapered portion at the sidethereof with the insulating layer.